1. Field
Thermal processing by scanning a substrate with a line of radiation.
2. Description of Related Art
The integrated circuit (IC) market is continually demanding greater memory capacity, faster switching speeds, and smaller feature sizes. One of the major steps the industry has taken to address these demands is to change from batch processing a substrate, such as a wafer (e.g., silicon wafer), in large furnaces to single substrate processing in a small chamber.
During single substrate processing, a substrate is typically heated to high temperatures so that various chemical and physical reactions can take place in multiple IC devices defined in the wafer. Of particular interest, favorable electrical performance of the IC devices requires implanted regions to be annealed. In general, annealing recreates a more crystalline structure from regions of a semiconductor substrate that were previously made amorphous, and activates dopants by incorporating their atoms into the crystalline lattice of the substrate. Thermal processes, such as annealing, require providing a relatively large amount of thermal energy to the substrate in a short amount of time, and thereafter rapidly cooling the substrate to terminate the thermal process. Examples of thermal processes currently in use include Rapid Thermal Processing (RTP) and impulse (spike) annealing. While such processes are widely used, current technology is not ideal. It tends to ramp the temperature of the substrate too slowly and expose the substrate to elevated temperatures for too long. These problems become more severe with increasing substrate sizes, increasing switching speeds, and/or decreasing feature sizes.
In general, these thermal processes heat a substrate under controlled conditions according to a predetermined thermal recipe. These thermal recipes fundamentally consist of: a temperature that the semiconductor substrate must be heated to; the rate of change of temperature, i.e., the temperature ramp-up and ramp-down rates; and the time that the thermal processing system remains at a particular temperature. For example, thermal recipes may require the substrate to be heated from room temperature to temperatures of 1200° C. or more, for processing times at each distinct temperature ranging up to 60 seconds or more.
Moreover, to meet certain objectives, such as minimal diffusion, the amount of time that a semiconductor substrate is subjected to high temperatures must be restricted. To accomplish this, the temperature ramp rates, both up and down, are preferably high. In other words, it is desirable to be able to adjust the temperature of the substrate from a low to a high temperature, or visa versa, in as short a time as possible.
The requirement for high temperature ramp rates led to the development of Rapid Thermal Processing (RTP), where typical temperature ramp-up rates range from 200 to 400° C./second (° C./s), as compared to 5 to 15° C./minute for conventional furnaces. Typical ramp-down rates are in the range of 80 to 150° C./s. A drawback of RTP is that it heats the entire substrate even though the circuit devices typically reside only in the top few microns of a semiconductor substrate (e.g., a silicon wafer). This limits how fast a substrate can be heated up and cooled down. Moreover, once the entire substrate is at an elevated temperature, heat can only dissipate into the surrounding space or structures. As a result, state of the art RTP systems struggle to achieve a 400° C./s ramp-up rate and a 150° C./s ramp-down rate.
One technique that appears promising for increasing IC device switching speeds perhaps while maintaining similar feature sizes is semiconductor on Insulator (SOI) technology. One SOI technology involves implanting an oxygen species into a semiconductor substrate and annealing the substrate to form an insulating layer at a depth of a few hundred to a few thousand Angstroms (Å) into the substrate, creating a monocrystalline semiconductor region above the insulator layer and a bulk semiconductor substrate below the insulating layer. The monocrystalline layer above the insulator layer may be used to form devices therein and thereon. In general, such devices may be made without all of the necessary implants (e.g., without well implants) that generally accompany conventional circuit device processing. Accordingly, switching speeds of the devices tend to be greater and limitations, such as leakage current, tend to be reduced.
The SOI process described above generally requires a RTP step to form the insulator layer. Representatively, as noted above, an oxygen species is implanted and a thermal annealing is performed to form the insulator layer through a process known as Otswald Ripening. One problem with such an SOI formation process is that the anneal time, using conventional RTP processing, tends to be too long to be commercially feasible.